8:1 multiplexer to 6:1 multiplexer











up vote
4
down vote

favorite












I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.






multiplexer







share|improve this question









New contributor




zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.




















  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    4 hours ago








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    4 hours ago






  • 1




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    4 hours ago












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    1 hour ago















up vote
4
down vote

favorite












I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.






multiplexer







share|improve this question









New contributor




zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.




















  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    4 hours ago








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    4 hours ago






  • 1




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    4 hours ago












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    1 hour ago













up vote
4
down vote

favorite









up vote
4
down vote

favorite











I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.






multiplexer







share|improve this question









New contributor




zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.











I have 6 inputs that I want to insert in a 8-1 multiplexer. I just want to know how to modify the 8-1 mux to support only 6 inputs. I mean the last two rows on the truth table of the 8-1 won't be available.



This is the 8-1 mux I am using:
enter image description here



and its logic table:



enter image description here



I only want to use the D0 to D5 inputs.






multiplexer




multiplexer






share|improve this question









New contributor




zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.











share|improve this question









New contributor




zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.









share|improve this question




share|improve this question








edited 2 hours ago









mike65535

9961619




9961619






New contributor




zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.









asked 4 hours ago









zaiz2s

211




211




New contributor




zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.





New contributor





zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.






zaiz2s is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.












  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    4 hours ago








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    4 hours ago






  • 1




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    4 hours ago












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    1 hour ago


















  • Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
    – Andy aka
    4 hours ago








  • 1




    You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
    – analogsystemsrf
    4 hours ago






  • 1




    Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
    – Eugene Sh.
    4 hours ago












  • Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
    – Harry Svensson
    1 hour ago
















Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
– Andy aka
4 hours ago






Then ensure that your selection inputs only produces numbers in the range 000 to 101. Go stufy modulo arithmetic.
– Andy aka
4 hours ago






1




1




You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
– analogsystemsrf
4 hours ago




You might tie the top 3 inputs together, thus 101,110, and 111 produce the same output. Will this confuse your state machine?
– analogsystemsrf
4 hours ago




1




1




Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
– Eugene Sh.
4 hours ago






Nothing in the MUX should be modified. It's the S-inputs who define. The S>=6 should be don't cares.
– Eugene Sh.
4 hours ago














Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
– Harry Svensson
1 hour ago




Instead of placing the enable on the inputs, perhaps you should put the enable on the output? Literally after the OR gate and before it forks into Y and Ỹ. Besides, are you sure that it is Y and Ỹ, shouldn't they be swapped?
– Harry Svensson
1 hour ago










1 Answer
1






active

oldest

votes

















up vote
6
down vote













Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






share|improve this answer





















    Your Answer





    StackExchange.ifUsing("editor", function () {
    return StackExchange.using("mathjaxEditing", function () {
    StackExchange.MarkdownEditor.creationCallbacks.add(function (editor, postfix) {
    StackExchange.mathjaxEditing.prepareWmdForMathJax(editor, postfix, [["\$", "\$"]]);
    });
    });
    }, "mathjax-editing");

    StackExchange.ifUsing("editor", function () {
    return StackExchange.using("schematics", function () {
    StackExchange.schematics.init();
    });
    }, "cicuitlab");

    StackExchange.ready(function() {
    var channelOptions = {
    tags: "".split(" "),
    id: "135"
    };
    initTagRenderer("".split(" "), "".split(" "), channelOptions);

    StackExchange.using("externalEditor", function() {
    // Have to fire editor after snippets, if snippets enabled
    if (StackExchange.settings.snippets.snippetsEnabled) {
    StackExchange.using("snippets", function() {
    createEditor();
    });
    }
    else {
    createEditor();
    }
    });

    function createEditor() {
    StackExchange.prepareEditor({
    heartbeatType: 'answer',
    convertImagesToLinks: false,
    noModals: true,
    showLowRepImageUploadWarning: true,
    reputationToPostImages: null,
    bindNavPrevention: true,
    postfix: "",
    imageUploader: {
    brandingHtml: "Powered by u003ca class="icon-imgur-white" href="https://imgur.com/"u003eu003c/au003e",
    contentPolicyHtml: "User contributions licensed under u003ca href="https://creativecommons.org/licenses/by-sa/3.0/"u003ecc by-sa 3.0 with attribution requiredu003c/au003e u003ca href="https://stackoverflow.com/legal/content-policy"u003e(content policy)u003c/au003e",
    allowUrls: true
    },
    onDemand: true,
    discardSelector: ".discard-answer"
    ,immediatelyShowMarkdownHelp:true
    });


    }
    });






    zaiz2s is a new contributor. Be nice, and check out our Code of Conduct.










    draft saved

    draft discarded


















    StackExchange.ready(
    function () {
    StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2felectronics.stackexchange.com%2fquestions%2f411858%2f81-multiplexer-to-61-multiplexer%23new-answer', 'question_page');
    }
    );

    Post as a guest















    Required, but never shown

























    1 Answer
    1






    active

    oldest

    votes








    1 Answer
    1






    active

    oldest

    votes









    active

    oldest

    votes






    active

    oldest

    votes








    up vote
    6
    down vote













    Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






    share|improve this answer

























      up vote
      6
      down vote













      Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






      share|improve this answer























        up vote
        6
        down vote










        up vote
        6
        down vote









        Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.






        share|improve this answer












        Assume that D6 and D7 are always low. Trace those signals through the gates in your design. If you find gates whose output values must always be the same, those gates can be removed and their output signals changed to a direct connection to logic '1' or '0'. Repeat until no gates are removed. Then remove unnecessary direct connections to logic '1' or '0'.







        share|improve this answer












        share|improve this answer



        share|improve this answer










        answered 4 hours ago









        Elliot Alderson

        4,5711918




        4,5711918






















            zaiz2s is a new contributor. Be nice, and check out our Code of Conduct.










            draft saved

            draft discarded


















            zaiz2s is a new contributor. Be nice, and check out our Code of Conduct.













            zaiz2s is a new contributor. Be nice, and check out our Code of Conduct.












            zaiz2s is a new contributor. Be nice, and check out our Code of Conduct.
















            Thanks for contributing an answer to Electrical Engineering Stack Exchange!


            • Please be sure to answer the question. Provide details and share your research!

            But avoid …



            • Asking for help, clarification, or responding to other answers.

            • Making statements based on opinion; back them up with references or personal experience.


            Use MathJax to format equations. MathJax reference.


            To learn more, see our tips on writing great answers.





            Some of your past answers have not been well-received, and you're in danger of being blocked from answering.


            Please pay close attention to the following guidance:


            • Please be sure to answer the question. Provide details and share your research!

            But avoid …



            • Asking for help, clarification, or responding to other answers.

            • Making statements based on opinion; back them up with references or personal experience.


            To learn more, see our tips on writing great answers.




            draft saved


            draft discarded














            StackExchange.ready(
            function () {
            StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2felectronics.stackexchange.com%2fquestions%2f411858%2f81-multiplexer-to-61-multiplexer%23new-answer', 'question_page');
            }
            );

            Post as a guest















            Required, but never shown





















































            Required, but never shown














            Required, but never shown












            Required, but never shown







            Required, but never shown

































            Required, but never shown














            Required, but never shown












            Required, but never shown







            Required, but never shown







            -

            Popular posts from this blog

            What visual should I use to simply compare current year value vs last year in Power BI desktop

            Image
            0 I have column SubToBind that shows current year ratio and column PY SubToBind which shows previous year ratio. How can I simply create a card that would be displaying them both in a nice way? Something like that: I cannot achieve that with regular card, I also tried Card with States by OKViz but also unable to see both values. In KPI visual - I dont like the word "Goal", it will confuse end users. Are there any cards or other visuals that would do the job? Thanks powerbi dax powerbi-embedded share | improve this question edited Jun 11 '18 at 20:11 Oleg ...
            Read more

            How to ignore python UserWarning in pytest?

            Image
            up vote 1 down vote favorite I am using openpyxl for parsing .xlsm files, and pytest for testing. When I open a file, I get the: OpenPyxl -> UserWarning: Data Validation extension is not supported and will be removed That is not really a problem bcs. program works and I can't change the .xlsm file to fix that. But... When I run pytest with something like: def test_wrong_file_format(): assert check_excel(open_excel('file.xlsm')) == True I will get the warning i mentioned altought check_excel(open_excel('file.xlsm')) returns True and the test should suceed... Is there a nice way to tell the pytest that "It's not a bug it's a feature" and tests should pass even when they get this warning? Is there other way than using something like: with pytest.warns(UserWarning): ...
            Read more

            Alexandru Averescu

            Image
            Alexandre Averescu Alexandru Averescu Naissance 3 avril 1859 Babele, Ismail  (ro) près de Izmaïl (principauté de Moldavie) Décès 2 octobre 1938 (à 79 ans) [ 1 ] Bucarest Origine   Roumanie Arme cavalerie Grade Maréchal Années de service 1901-1917 Commandement chef d'état-major général 2 e  armée 3 e  armée Groupe d'armée sud armée du Danube Conflits Guerre russo-turque de 1877-1878 Deuxième guerre balkanique Première Guerre mondiale Faits d'armes Bataille de Turtucaia/Tutrakan Bataille de Mărăști Distinctions Autres fonctions 3 fois président du Conseil des ministres ministre des Affaires étrangères ministre sans portefeuille conseiller de la Couronne modifier   Alexandre Averescu (en roumain : Alexandru Averescu .mw-parser-output .prononciation>a{background:url("//upload.wikimedia.org/wikipedia/commons/thumb/8/8a/Loudspeaker.svg/11px-Loudspeaker.svg.png")center ...
            Read more