Qualifying SVA's ##[0:$] in a simulation











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I have the following SVA property:



$rose(hresetn) |-> (

        ##[0:$] $rose(signal_a)

        ##[0:2] ($rose(signal_b));


During a simulation if signal_a never rose (which is functionally acceptable), will my test finish with an error ? Do simulators qualify ##[0:$] as an error/violation if it never happened during run-time, or it will be treated as a property never satisfied ?



Thanks.






system-verilog uvm system-verilog-assertions







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    have you tried?
    – Serge
    Nov 22 at 19:49















up vote
-1
down vote

favorite












I have the following SVA property:



$rose(hresetn) |-> (

        ##[0:$] $rose(signal_a)

        ##[0:2] ($rose(signal_b));


During a simulation if signal_a never rose (which is functionally acceptable), will my test finish with an error ? Do simulators qualify ##[0:$] as an error/violation if it never happened during run-time, or it will be treated as a property never satisfied ?



Thanks.






system-verilog uvm system-verilog-assertions







share|improve this question


















  • 1




    have you tried?
    – Serge
    Nov 22 at 19:49













up vote
-1
down vote

favorite









up vote
-1
down vote

favorite











I have the following SVA property:



$rose(hresetn) |-> (

        ##[0:$] $rose(signal_a)

        ##[0:2] ($rose(signal_b));


During a simulation if signal_a never rose (which is functionally acceptable), will my test finish with an error ? Do simulators qualify ##[0:$] as an error/violation if it never happened during run-time, or it will be treated as a property never satisfied ?



Thanks.






system-verilog uvm system-verilog-assertions







share|improve this question













I have the following SVA property:



$rose(hresetn) |-> (

        ##[0:$] $rose(signal_a)

        ##[0:2] ($rose(signal_b));


During a simulation if signal_a never rose (which is functionally acceptable), will my test finish with an error ? Do simulators qualify ##[0:$] as an error/violation if it never happened during run-time, or it will be treated as a property never satisfied ?



Thanks.






system-verilog uvm system-verilog-assertions




system-verilog uvm system-verilog-assertions






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asked Nov 22 at 15:39









El_Gahaf

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84








  • 1




    have you tried?
    – Serge
    Nov 22 at 19:49














  • 1




    have you tried?
    – Serge
    Nov 22 at 19:49








1




1




have you tried?
– Serge
Nov 22 at 19:49




have you tried?
– Serge
Nov 22 at 19:49












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SystemVerilog has both weak and strong properties. By default, everything is weak meaning no match is just an incomplete assertion the neither passes or fails. Some tools can report any assertion attempt that has never completed. But there is also a strong property qualifier that will report an error if there is no match to a sequence by the end of simulation. (Note not all tools have implemented this feature)






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    SystemVerilog has both weak and strong properties. By default, everything is weak meaning no match is just an incomplete assertion the neither passes or fails. Some tools can report any assertion attempt that has never completed. But there is also a strong property qualifier that will report an error if there is no match to a sequence by the end of simulation. (Note not all tools have implemented this feature)






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      down vote













      SystemVerilog has both weak and strong properties. By default, everything is weak meaning no match is just an incomplete assertion the neither passes or fails. Some tools can report any assertion attempt that has never completed. But there is also a strong property qualifier that will report an error if there is no match to a sequence by the end of simulation. (Note not all tools have implemented this feature)






      share|improve this answer























        up vote
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        up vote
        0
        down vote









        SystemVerilog has both weak and strong properties. By default, everything is weak meaning no match is just an incomplete assertion the neither passes or fails. Some tools can report any assertion attempt that has never completed. But there is also a strong property qualifier that will report an error if there is no match to a sequence by the end of simulation. (Note not all tools have implemented this feature)






        share|improve this answer












        SystemVerilog has both weak and strong properties. By default, everything is weak meaning no match is just an incomplete assertion the neither passes or fails. Some tools can report any assertion attempt that has never completed. But there is also a strong property qualifier that will report an error if there is no match to a sequence by the end of simulation. (Note not all tools have implemented this feature)







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        answered Nov 25 at 4:58









        dave_59

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