Qfyilyi

For some time I have been using the DWT cycle counter, CYCCNT in STM32F4 processors for timing operations. Everywhere I look, the assumption is that this is a 32 bit counter.

However, I am now using the STM32F411CE processor and it looks to me like there are only 31 bits.
I run this code:

CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;

DWT->CTRL |= 1; 

uint32_t next = millis()+200;

DWT->CYCCNT = 0;

while(1){

  while(next > millis()){

  // do nothing

  }

  next += 200;

  printf("%8lu %12lun",next,DWT->CYCCNT);

}

And observe the results on the terminal. The processor is running at 100MHz, so the counter increases by 20 million after 200ms. After a while the counter value wraps but it wraps at 2^31, not 2^32:

21435   2039916353

21635   2059916353

21835   2079916353

22035   2099916353

22235   2119916353

22435   2139916341

22635     12432705

22835     32432705

23035     52432705

23235     72432705

So, can anyone point me to any definitive information about the CYCCNT counter width on the STM32F411 processor? Or have I overlooked something embarrassingly simple?

UPDATE:

I ran the exact same code on a board containing an STM32F405 processor and got these results:

30419   4204732031

30619   4233532031

30819   4262332031

31019   4291132031

31219     24964735

31419     53764738

31619     82564738

31819    111364735

So it seems clear to me that the '405 processor CYCCNT register is 32 bit whereas the '411 processor is only 31 bit. Most odd!

UPDATE2:

A second board with the same processor type behaves perfectly as well. A friend also ran the code on his (different) '411 board with no problems. It now seems that the board itself is faulty or, possibly, the processor is broken. All the other processor functions appear correct. Looks like it is just time to swap out the processor.

The description of DWT_CYCCNT is in section C1.8.8 of the Arm V7m Architecture Reference manual which you can get from here

Section C1.8.3 says

CYCCNT is an optional free-running 32-bit cycle counter.

When implemented and enabled, CYCCNT increments on each cycle of the processor clock. When the counter
overflows it wraps to zero, transparently.

So this doesn't explain your findings.